summaryrefslogtreecommitdiff
path: root/Core/Src
diff options
context:
space:
mode:
Diffstat (limited to 'Core/Src')
-rwxr-xr-xCore/Src/fmc.c310
-rwxr-xr-xCore/Src/gpio.c117
-rwxr-xr-xCore/Src/i2c.c131
-rwxr-xr-xCore/Src/main.c286
-rwxr-xr-xCore/Src/quadspi.c160
-rwxr-xr-xCore/Src/sai.c179
-rwxr-xr-xCore/Src/stm32h7xx_hal_msp.c80
-rwxr-xr-xCore/Src/stm32h7xx_it.c245
-rwxr-xr-xCore/Src/syscalls.c176
-rwxr-xr-xCore/Src/sysmem.c79
-rwxr-xr-xCore/Src/system_stm32h7xx.c557
11 files changed, 2320 insertions, 0 deletions
diff --git a/Core/Src/fmc.c b/Core/Src/fmc.c
new file mode 100755
index 0000000..ae14948
--- /dev/null
+++ b/Core/Src/fmc.c
@@ -0,0 +1,310 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name : FMC.c
+ * Description : This file provides code for the configuration
+ * of the FMC peripheral.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "fmc.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SDRAM_HandleTypeDef hsdram1;
+
+/* FMC initialization function */
+void MX_FMC_Init(void)
+{
+ /* USER CODE BEGIN FMC_Init 0 */
+
+ /* USER CODE END FMC_Init 0 */
+
+ FMC_SDRAM_TimingTypeDef SdramTiming = {0};
+
+ /* USER CODE BEGIN FMC_Init 1 */
+
+ /* USER CODE END FMC_Init 1 */
+
+ /** Perform the SDRAM1 memory initialization sequence
+ */
+ hsdram1.Instance = FMC_SDRAM_DEVICE;
+ /* hsdram1.Init */
+ hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
+ hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
+ hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
+ hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
+ hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
+ hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
+ hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
+ hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
+ hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
+ hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
+ /* SdramTiming */
+ SdramTiming.LoadToActiveDelay = 16;
+ SdramTiming.ExitSelfRefreshDelay = 12;
+ SdramTiming.SelfRefreshTime = 16;
+ SdramTiming.RowCycleDelay = 10;
+ SdramTiming.WriteRecoveryTime = 16;
+ SdramTiming.RPDelay = 3;
+ SdramTiming.RCDDelay = 3;
+
+ if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
+ {
+ Error_Handler( );
+ }
+
+ /* USER CODE BEGIN FMC_Init 2 */
+
+ /* USER CODE END FMC_Init 2 */
+}
+
+static uint32_t FMC_Initialized = 0;
+
+static void HAL_FMC_MspInit(void){
+ /* USER CODE BEGIN FMC_MspInit 0 */
+
+ /* USER CODE END FMC_MspInit 0 */
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if (FMC_Initialized) {
+ return;
+ }
+ FMC_Initialized = 1;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC;
+ PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_FMC_CLK_ENABLE();
+
+ /** FMC GPIO Configuration
+ PF0 ------> FMC_A0
+ PF1 ------> FMC_A1
+ PF2 ------> FMC_A2
+ PF3 ------> FMC_A3
+ PF4 ------> FMC_A4
+ PF5 ------> FMC_A5
+ PA7 ------> FMC_SDNWE
+ PC4 ------> FMC_SDNE0
+ PC5 ------> FMC_SDCKE0
+ PF11 ------> FMC_SDNRAS
+ PF12 ------> FMC_A6
+ PF13 ------> FMC_A7
+ PF14 ------> FMC_A8
+ PF15 ------> FMC_A9
+ PG0 ------> FMC_A10
+ PG1 ------> FMC_A11
+ PE7 ------> FMC_D4
+ PE8 ------> FMC_D5
+ PE9 ------> FMC_D6
+ PE10 ------> FMC_D7
+ PE11 ------> FMC_D8
+ PE12 ------> FMC_D9
+ PE13 ------> FMC_D10
+ PE14 ------> FMC_D11
+ PE15 ------> FMC_D12
+ PD8 ------> FMC_D13
+ PD9 ------> FMC_D14
+ PD10 ------> FMC_D15
+ PD14 ------> FMC_D0
+ PD15 ------> FMC_D1
+ PG2 ------> FMC_A12
+ PG4 ------> FMC_BA0
+ PG5 ------> FMC_BA1
+ PG8 ------> FMC_SDCLK
+ PD0 ------> FMC_D2
+ PD1 ------> FMC_D3
+ PG15 ------> FMC_SDNCAS
+ PE0 ------> FMC_NBL0
+ PE1 ------> FMC_NBL1
+ */
+ /* GPIO_InitStruct */
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
+ |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ /* GPIO_InitStruct */
+ GPIO_InitStruct.Pin = GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* GPIO_InitStruct */
+ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /* GPIO_InitStruct */
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
+ |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ /* GPIO_InitStruct */
+ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
+ |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
+ |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ /* GPIO_InitStruct */
+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
+ |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN FMC_MspInit 1 */
+
+ /* USER CODE END FMC_MspInit 1 */
+}
+
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* sdramHandle){
+ /* USER CODE BEGIN SDRAM_MspInit 0 */
+
+ /* USER CODE END SDRAM_MspInit 0 */
+ HAL_FMC_MspInit();
+ /* USER CODE BEGIN SDRAM_MspInit 1 */
+
+ /* USER CODE END SDRAM_MspInit 1 */
+}
+
+static uint32_t FMC_DeInitialized = 0;
+
+static void HAL_FMC_MspDeInit(void){
+ /* USER CODE BEGIN FMC_MspDeInit 0 */
+
+ /* USER CODE END FMC_MspDeInit 0 */
+ if (FMC_DeInitialized) {
+ return;
+ }
+ FMC_DeInitialized = 1;
+ /* Peripheral clock enable */
+ __HAL_RCC_FMC_CLK_DISABLE();
+
+ /** FMC GPIO Configuration
+ PF0 ------> FMC_A0
+ PF1 ------> FMC_A1
+ PF2 ------> FMC_A2
+ PF3 ------> FMC_A3
+ PF4 ------> FMC_A4
+ PF5 ------> FMC_A5
+ PA7 ------> FMC_SDNWE
+ PC4 ------> FMC_SDNE0
+ PC5 ------> FMC_SDCKE0
+ PF11 ------> FMC_SDNRAS
+ PF12 ------> FMC_A6
+ PF13 ------> FMC_A7
+ PF14 ------> FMC_A8
+ PF15 ------> FMC_A9
+ PG0 ------> FMC_A10
+ PG1 ------> FMC_A11
+ PE7 ------> FMC_D4
+ PE8 ------> FMC_D5
+ PE9 ------> FMC_D6
+ PE10 ------> FMC_D7
+ PE11 ------> FMC_D8
+ PE12 ------> FMC_D9
+ PE13 ------> FMC_D10
+ PE14 ------> FMC_D11
+ PE15 ------> FMC_D12
+ PD8 ------> FMC_D13
+ PD9 ------> FMC_D14
+ PD10 ------> FMC_D15
+ PD14 ------> FMC_D0
+ PD15 ------> FMC_D1
+ PG2 ------> FMC_A12
+ PG4 ------> FMC_BA0
+ PG5 ------> FMC_BA1
+ PG8 ------> FMC_SDCLK
+ PD0 ------> FMC_D2
+ PD1 ------> FMC_D3
+ PG15 ------> FMC_SDNCAS
+ PE0 ------> FMC_NBL0
+ PE1 ------> FMC_NBL1
+ */
+
+ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
+ |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
+
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7);
+
+ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5);
+
+ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
+ |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15);
+
+ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
+ |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
+ |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
+
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
+ |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
+
+ /* USER CODE BEGIN FMC_MspDeInit 1 */
+
+ /* USER CODE END FMC_MspDeInit 1 */
+}
+
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* sdramHandle){
+ /* USER CODE BEGIN SDRAM_MspDeInit 0 */
+
+ /* USER CODE END SDRAM_MspDeInit 0 */
+ HAL_FMC_MspDeInit();
+ /* USER CODE BEGIN SDRAM_MspDeInit 1 */
+
+ /* USER CODE END SDRAM_MspDeInit 1 */
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c
new file mode 100755
index 0000000..ad7713a
--- /dev/null
+++ b/Core/Src/gpio.c
@@ -0,0 +1,117 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file gpio.c
+ * @brief This file provides code for the configuration
+ * of all used GPIO pins.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gpio.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure GPIO */
+/*----------------------------------------------------------------------------*/
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/** Configure pins
+ PH0-OSC_IN (PH0) ------> RCC_OSC_IN
+ PA13 (JTMS/SWDIO) ------> DEBUG_JTMS-SWDIO
+ PA14 (JTCK/SWCLK) ------> DEBUG_JTCK-SWCLK
+ PB3 (JTDO/TRACESWO) ------> DEBUG_JTDO-SWO
+*/
+void MX_GPIO_Init(void)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIO_OUT8_GPIO_Port, GPIO_OUT8_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOC, GPIO_OUT7_Pin|GPIO_OUT6_Pin|GPIO_OUT3_Pin|GPIO_OUT2_Pin
+ |GPIO_OUT1_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOD, GPIO_OUT4_Pin|GPIO_OUT5_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(CS4272_NRST_GPIO_Port, CS4272_NRST_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin : GPIO_OUT8_Pin */
+ GPIO_InitStruct.Pin = GPIO_OUT8_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIO_OUT8_GPIO_Port, &GPIO_InitStruct);
+
+ /*Configure GPIO pins : GPIO_OUT7_Pin GPIO_OUT6_Pin GPIO_OUT3_Pin GPIO_OUT2_Pin
+ GPIO_OUT1_Pin */
+ GPIO_InitStruct.Pin = GPIO_OUT7_Pin|GPIO_OUT6_Pin|GPIO_OUT3_Pin|GPIO_OUT2_Pin
+ |GPIO_OUT1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /*Configure GPIO pins : GPIO_IN8_Pin GPIO_IN7_Pin */
+ GPIO_InitStruct.Pin = GPIO_IN8_Pin|GPIO_IN7_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /*Configure GPIO pins : GPIO_IN6_Pin GPIO_IN5_Pin GPIO_IN4_Pin GPIO_IN3_Pin
+ GPIO_IN2_Pin GPIO_IN1_Pin */
+ GPIO_InitStruct.Pin = GPIO_IN6_Pin|GPIO_IN5_Pin|GPIO_IN4_Pin|GPIO_IN3_Pin
+ |GPIO_IN2_Pin|GPIO_IN1_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /*Configure GPIO pins : GPIO_OUT4_Pin GPIO_OUT5_Pin */
+ GPIO_InitStruct.Pin = GPIO_OUT4_Pin|GPIO_OUT5_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ /*Configure GPIO pin : CS4272_NRST_Pin */
+ GPIO_InitStruct.Pin = CS4272_NRST_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(CS4272_NRST_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
diff --git a/Core/Src/i2c.c b/Core/Src/i2c.c
new file mode 100755
index 0000000..6ebfe13
--- /dev/null
+++ b/Core/Src/i2c.c
@@ -0,0 +1,131 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file i2c.c
+ * @brief This file provides code for the configuration
+ * of the I2C instances.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "i2c.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+I2C_HandleTypeDef hi2c4;
+
+/* I2C4 init function */
+void MX_I2C4_Init(void)
+{
+
+ /* USER CODE BEGIN I2C4_Init 0 */
+
+ /* USER CODE END I2C4_Init 0 */
+
+ /* USER CODE BEGIN I2C4_Init 1 */
+
+ /* USER CODE END I2C4_Init 1 */
+ hi2c4.Instance = I2C4;
+ hi2c4.Init.Timing = 0x00201E2D;
+ hi2c4.Init.OwnAddress1 = 0;
+ hi2c4.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ hi2c4.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+ hi2c4.Init.OwnAddress2 = 0;
+ hi2c4.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ hi2c4.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+ hi2c4.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+ if (HAL_I2C_Init(&hi2c4) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Configure Analogue filter
+ */
+ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c4, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Configure Digital filter
+ */
+ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c4, 0) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN I2C4_Init 2 */
+
+ /* USER CODE END I2C4_Init 2 */
+
+}
+
+void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(i2cHandle->Instance==I2C4)
+ {
+ /* USER CODE BEGIN I2C4_MspInit 0 */
+
+ /* USER CODE END I2C4_MspInit 0 */
+
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ /**I2C4 GPIO Configuration
+ PB8 ------> I2C4_SCL
+ PB9 ------> I2C4_SDA
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF6_I2C4;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ /* I2C4 clock enable */
+ __HAL_RCC_I2C4_CLK_ENABLE();
+ /* USER CODE BEGIN I2C4_MspInit 1 */
+
+ /* USER CODE END I2C4_MspInit 1 */
+ }
+}
+
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)
+{
+
+ if(i2cHandle->Instance==I2C4)
+ {
+ /* USER CODE BEGIN I2C4_MspDeInit 0 */
+
+ /* USER CODE END I2C4_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_I2C4_CLK_DISABLE();
+
+ /**I2C4 GPIO Configuration
+ PB8 ------> I2C4_SCL
+ PB9 ------> I2C4_SDA
+ */
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8);
+
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9);
+
+ /* USER CODE BEGIN I2C4_MspDeInit 1 */
+
+ /* USER CODE END I2C4_MspDeInit 1 */
+ }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
diff --git a/Core/Src/main.c b/Core/Src/main.c
new file mode 100755
index 0000000..721e51c
--- /dev/null
+++ b/Core/Src/main.c
@@ -0,0 +1,286 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "i2c.h"
+#include "quadspi.h"
+#include "sai.h"
+#include "usb_device.h"
+#include "gpio.h"
+#include "fmc.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+void PeriphCommonClock_Config(void);
+static void MPU_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+
+ /* USER CODE BEGIN 1 */
+
+ // disabled by the boot loader
+ __enable_irq();
+
+ /* USER CODE END 1 */
+
+ /* MPU Configuration--------------------------------------------------------*/
+ MPU_Config();
+
+ /* Enable the CPU Cache */
+
+ /* Enable I-Cache---------------------------------------------------------*/
+ SCB_EnableICache();
+
+ /* Enable D-Cache---------------------------------------------------------*/
+ SCB_EnableDCache();
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+
+ /* Configure the peripherals common clocks */
+// PeriphCommonClock_Config();
+
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_FMC_Init();
+ MX_I2C4_Init();
+ MX_SAI1_Init();
+ MX_USB_DEVICE_Init();
+// MX_QUADSPI_Init();
+ /* USER CODE BEGIN 2 */
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_12, GPIO_PIN_SET);
+
+ HAL_Delay(1000);
+
+ HAL_GPIO_WritePin(GPIOC, GPIO_PIN_12, GPIO_PIN_RESET);
+
+ HAL_Delay(1000);
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Supply configuration update enable
+ */
+ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 5;
+ RCC_OscInitStruct.PLL.PLLN = 192;
+ RCC_OscInitStruct.PLL.PLLP = 2;
+ RCC_OscInitStruct.PLL.PLLQ = 15;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+ |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+ RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/**
+ * @brief Peripherals Common Clock Configuration
+ * @retval None
+ */
+void PeriphCommonClock_Config(void)
+{
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C4|RCC_PERIPHCLK_SAI1;
+ PeriphClkInitStruct.PLL3.PLL3M = 5;
+ PeriphClkInitStruct.PLL3.PLL3N = 49;
+ PeriphClkInitStruct.PLL3.PLL3P = 20;
+ PeriphClkInitStruct.PLL3.PLL3Q = 5;
+ PeriphClkInitStruct.PLL3.PLL3R = 30;
+ PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2;
+ PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
+ PeriphClkInitStruct.PLL3.PLL3FRACN = 1246;
+ PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL3;
+ PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+ /* MPU Configuration */
+
+void MPU_Config(void)
+{
+ MPU_Region_InitTypeDef MPU_InitStruct = {0};
+
+ /* Disables the MPU */
+ HAL_MPU_Disable();
+
+ /** Initializes and configures the Region and the memory to be protected
+ */
+ MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+ MPU_InitStruct.Number = MPU_REGION_NUMBER0;
+ MPU_InitStruct.BaseAddress = 0x90000000;
+ MPU_InitStruct.Size = MPU_REGION_SIZE_16MB;
+ MPU_InitStruct.SubRegionDisable = 0x0;
+ MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+ MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+ MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
+ MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+
+ HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ /* Enables the MPU */
+ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+}
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/Core/Src/quadspi.c b/Core/Src/quadspi.c
new file mode 100755
index 0000000..8572981
--- /dev/null
+++ b/Core/Src/quadspi.c
@@ -0,0 +1,160 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file quadspi.c
+ * @brief This file provides code for the configuration
+ * of the QUADSPI instances.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "quadspi.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+QSPI_HandleTypeDef hqspi;
+
+/* QUADSPI init function */
+void MX_QUADSPI_Init(void)
+{
+
+ /* USER CODE BEGIN QUADSPI_Init 0 */
+
+ /* USER CODE END QUADSPI_Init 0 */
+
+ /* USER CODE BEGIN QUADSPI_Init 1 */
+
+ /* USER CODE END QUADSPI_Init 1 */
+ hqspi.Instance = QUADSPI;
+ hqspi.Init.ClockPrescaler = 2;
+ hqspi.Init.FifoThreshold = 4;
+ hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
+ hqspi.Init.FlashSize = 23;
+ hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE;
+ hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
+ hqspi.Init.FlashID = QSPI_FLASH_ID_1;
+ hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
+ if (HAL_QSPI_Init(&hqspi) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN QUADSPI_Init 2 */
+
+ /* USER CODE END QUADSPI_Init 2 */
+
+}
+
+void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ if(qspiHandle->Instance==QUADSPI)
+ {
+ /* USER CODE BEGIN QUADSPI_MspInit 0 */
+
+ /* USER CODE END QUADSPI_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_QSPI;
+ PeriphClkInitStruct.PLL2.PLL2M = 2;
+ PeriphClkInitStruct.PLL2.PLL2N = 16;
+ PeriphClkInitStruct.PLL2.PLL2P = 2;
+ PeriphClkInitStruct.PLL2.PLL2Q = 2;
+ PeriphClkInitStruct.PLL2.PLL2R = 1;
+ PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
+ PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
+ PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
+ PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* QUADSPI clock enable */
+ __HAL_RCC_QSPI_CLK_ENABLE();
+
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ /**QUADSPI GPIO Configuration
+ PF6 ------> QUADSPI_BK1_IO3
+ PF7 ------> QUADSPI_BK1_IO2
+ PF8 ------> QUADSPI_BK1_IO0
+ PF9 ------> QUADSPI_BK1_IO1
+ PF10 ------> QUADSPI_CLK
+ PG6 ------> QUADSPI_BK1_NCS
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN QUADSPI_MspInit 1 */
+
+ /* USER CODE END QUADSPI_MspInit 1 */
+ }
+}
+
+void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* qspiHandle)
+{
+
+ if(qspiHandle->Instance==QUADSPI)
+ {
+ /* USER CODE BEGIN QUADSPI_MspDeInit 0 */
+
+ /* USER CODE END QUADSPI_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_QSPI_CLK_DISABLE();
+
+ /**QUADSPI GPIO Configuration
+ PF6 ------> QUADSPI_BK1_IO3
+ PF7 ------> QUADSPI_BK1_IO2
+ PF8 ------> QUADSPI_BK1_IO0
+ PF9 ------> QUADSPI_BK1_IO1
+ PF10 ------> QUADSPI_CLK
+ PG6 ------> QUADSPI_BK1_NCS
+ */
+ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9
+ |GPIO_PIN_10);
+
+ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6);
+
+ /* USER CODE BEGIN QUADSPI_MspDeInit 1 */
+
+ /* USER CODE END QUADSPI_MspDeInit 1 */
+ }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
diff --git a/Core/Src/sai.c b/Core/Src/sai.c
new file mode 100755
index 0000000..9bd58d9
--- /dev/null
+++ b/Core/Src/sai.c
@@ -0,0 +1,179 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * File Name : SAI.c
+ * Description : This file provides code for the configuration
+ * of the SAI instances.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "sai.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SAI_HandleTypeDef hsai_BlockA1;
+SAI_HandleTypeDef hsai_BlockB1;
+
+/* SAI1 init function */
+void MX_SAI1_Init(void)
+{
+
+ /* USER CODE BEGIN SAI1_Init 0 */
+
+ /* USER CODE END SAI1_Init 0 */
+
+ /* USER CODE BEGIN SAI1_Init 1 */
+
+ /* USER CODE END SAI1_Init 1 */
+
+ /* USER CODE BEGIN SAI1_Init 1 */
+
+ /* USER CODE END SAI1_Init 1 */
+
+ hsai_BlockA1.Instance = SAI1_Block_A;
+ hsai_BlockA1.Init.AudioMode = SAI_MODEMASTER_TX;
+ hsai_BlockA1.Init.Synchro = SAI_ASYNCHRONOUS;
+ hsai_BlockA1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE;
+ hsai_BlockA1.Init.NoDivider = SAI_MCK_OVERSAMPLING_DISABLE;
+ hsai_BlockA1.Init.MckOverSampling = SAI_MCK_OVERSAMPLING_DISABLE;
+ hsai_BlockA1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY;
+ hsai_BlockA1.Init.AudioFrequency = SAI_AUDIO_FREQUENCY_192K;
+ hsai_BlockA1.Init.SynchroExt = SAI_SYNCEXT_DISABLE;
+ hsai_BlockA1.Init.MonoStereoMode = SAI_STEREOMODE;
+ hsai_BlockA1.Init.CompandingMode = SAI_NOCOMPANDING;
+ hsai_BlockA1.Init.TriState = SAI_OUTPUT_NOTRELEASED;
+ if (HAL_SAI_InitProtocol(&hsai_BlockA1, SAI_I2S_STANDARD, SAI_PROTOCOL_DATASIZE_24BIT, 2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ hsai_BlockB1.Instance = SAI1_Block_B;
+ hsai_BlockB1.Init.AudioMode = SAI_MODESLAVE_RX;
+ hsai_BlockB1.Init.Synchro = SAI_SYNCHRONOUS;
+ hsai_BlockB1.Init.OutputDrive = SAI_OUTPUTDRIVE_DISABLE;
+ hsai_BlockB1.Init.MckOverSampling = SAI_MCK_OVERSAMPLING_DISABLE;
+ hsai_BlockB1.Init.FIFOThreshold = SAI_FIFOTHRESHOLD_EMPTY;
+ hsai_BlockB1.Init.SynchroExt = SAI_SYNCEXT_DISABLE;
+ hsai_BlockB1.Init.MonoStereoMode = SAI_STEREOMODE;
+ hsai_BlockB1.Init.CompandingMode = SAI_NOCOMPANDING;
+ hsai_BlockB1.Init.TriState = SAI_OUTPUT_NOTRELEASED;
+ if (HAL_SAI_InitProtocol(&hsai_BlockB1, SAI_I2S_STANDARD, SAI_PROTOCOL_DATASIZE_24BIT, 2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN SAI1_Init 2 */
+
+ /* USER CODE END SAI1_Init 2 */
+
+}
+static uint32_t SAI1_client =0;
+
+void HAL_SAI_MspInit(SAI_HandleTypeDef* saiHandle)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct;
+/* SAI1 */
+ if(saiHandle->Instance==SAI1_Block_A)
+ {
+ /* SAI1 clock enable */
+ if (SAI1_client == 0)
+ {
+ __HAL_RCC_SAI1_CLK_ENABLE();
+ }
+ SAI1_client ++;
+
+ /**SAI1_A_Block_A GPIO Configuration
+ PE2 ------> SAI1_MCLK_A
+ PE4 ------> SAI1_FS_A
+ PE5 ------> SAI1_SCK_A
+ PE6 ------> SAI1_SD_A
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF6_SAI1;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ }
+ if(saiHandle->Instance==SAI1_Block_B)
+ {
+ /* SAI1 clock enable */
+ if (SAI1_client == 0)
+ {
+ __HAL_RCC_SAI1_CLK_ENABLE();
+ }
+ SAI1_client ++;
+
+ /**SAI1_B_Block_B GPIO Configuration
+ PE3 ------> SAI1_SD_B
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_3;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF6_SAI1;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ }
+}
+
+void HAL_SAI_MspDeInit(SAI_HandleTypeDef* saiHandle)
+{
+
+/* SAI1 */
+ if(saiHandle->Instance==SAI1_Block_A)
+ {
+ SAI1_client --;
+ if (SAI1_client == 0)
+ {
+ /* Peripheral clock disable */
+ __HAL_RCC_SAI1_CLK_DISABLE();
+ }
+
+ /**SAI1_A_Block_A GPIO Configuration
+ PE2 ------> SAI1_MCLK_A
+ PE4 ------> SAI1_FS_A
+ PE5 ------> SAI1_SCK_A
+ PE6 ------> SAI1_SD_A
+ */
+ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6);
+
+ }
+ if(saiHandle->Instance==SAI1_Block_B)
+ {
+ SAI1_client --;
+ if (SAI1_client == 0)
+ {
+ /* Peripheral clock disable */
+ __HAL_RCC_SAI1_CLK_DISABLE();
+ }
+
+ /**SAI1_B_Block_B GPIO Configuration
+ PE3 ------> SAI1_SD_B
+ */
+ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_3);
+
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/Core/Src/stm32h7xx_hal_msp.c b/Core/Src/stm32h7xx_hal_msp.c
new file mode 100755
index 0000000..8fc7789
--- /dev/null
+++ b/Core/Src/stm32h7xx_hal_msp.c
@@ -0,0 +1,80 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_msp.c
+ * @brief This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* System interrupt init*/
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/stm32h7xx_it.c b/Core/Src/stm32h7xx_it.c
new file mode 100755
index 0000000..c4cb071
--- /dev/null
+++ b/Core/Src/stm32h7xx_it.c
@@ -0,0 +1,245 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7xx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32h7xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ {
+ }
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ /* USER CODE BEGIN SVCall_IRQn 0 */
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ /* USER CODE BEGIN PendSV_IRQn 0 */
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32H7xx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32h7xx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles USB On The Go HS End Point 1 Out global interrupt.
+ */
+void OTG_HS_EP1_OUT_IRQHandler(void)
+{
+ /* USER CODE BEGIN OTG_HS_EP1_OUT_IRQn 0 */
+
+ /* USER CODE END OTG_HS_EP1_OUT_IRQn 0 */
+ HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS);
+ /* USER CODE BEGIN OTG_HS_EP1_OUT_IRQn 1 */
+
+ /* USER CODE END OTG_HS_EP1_OUT_IRQn 1 */
+}
+
+/**
+ * @brief This function handles USB On The Go HS End Point 1 In global interrupt.
+ */
+void OTG_HS_EP1_IN_IRQHandler(void)
+{
+ /* USER CODE BEGIN OTG_HS_EP1_IN_IRQn 0 */
+
+ /* USER CODE END OTG_HS_EP1_IN_IRQn 0 */
+ HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS);
+ /* USER CODE BEGIN OTG_HS_EP1_IN_IRQn 1 */
+
+ /* USER CODE END OTG_HS_EP1_IN_IRQn 1 */
+}
+
+/**
+ * @brief This function handles USB OTG HS global interrupt.
+ */
+void OTG_HS_IRQHandler(void)
+{
+ /* USER CODE BEGIN OTG_HS_IRQn 0 */
+
+ /* USER CODE END OTG_HS_IRQn 0 */
+ HAL_PCD_IRQHandler(&hpcd_USB_OTG_HS);
+ /* USER CODE BEGIN OTG_HS_IRQn 1 */
+
+ /* USER CODE END OTG_HS_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c
new file mode 100755
index 0000000..0197f26
--- /dev/null
+++ b/Core/Src/syscalls.c
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * @file syscalls.c
+ * @author Auto-generated by STM32CubeIDE
+ * @brief STM32CubeIDE Minimal System calls file
+ *
+ * For more information about which c-functions
+ * need which of these lowlevel functions
+ * please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2020-2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+ return 1;
+}
+
+int _kill(int pid, int sig)
+{
+ (void)pid;
+ (void)sig;
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit (int status)
+{
+ _kill(status, -1);
+ while (1) {} /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+ (void)file;
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ *ptr++ = __io_getchar();
+ }
+
+ return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+ (void)file;
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ __io_putchar(*ptr++);
+ }
+ return len;
+}
+
+int _close(int file)
+{
+ (void)file;
+ return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+ (void)file;
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _isatty(int file)
+{
+ (void)file;
+ return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+ (void)file;
+ (void)ptr;
+ (void)dir;
+ return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+ (void)path;
+ (void)flags;
+ /* Pretend like we always fail */
+ return -1;
+}
+
+int _wait(int *status)
+{
+ (void)status;
+ errno = ECHILD;
+ return -1;
+}
+
+int _unlink(char *name)
+{
+ (void)name;
+ errno = ENOENT;
+ return -1;
+}
+
+int _times(struct tms *buf)
+{
+ (void)buf;
+ return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+ (void)file;
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _link(char *old, char *new)
+{
+ (void)old;
+ (void)new;
+ errno = EMLINK;
+ return -1;
+}
+
+int _fork(void)
+{
+ errno = EAGAIN;
+ return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+ (void)name;
+ (void)argv;
+ (void)env;
+ errno = ENOMEM;
+ return -1;
+}
diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c
new file mode 100755
index 0000000..23ea8e0
--- /dev/null
+++ b/Core/Src/sysmem.c
@@ -0,0 +1,79 @@
+/**
+ ******************************************************************************
+ * @file sysmem.c
+ * @author Generated by STM32CubeIDE
+ * @brief STM32CubeIDE System Memory calls file
+ *
+ * For more information about which C functions
+ * need which of these lowlevel functions
+ * please consult the newlib libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <errno.h>
+#include <stdint.h>
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ * and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * # .data # .bss # newlib heap # MSP stack #
+ * # # # # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start ^-- _end _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+ extern uint8_t _end; /* Symbol defined in the linker script */
+ extern uint8_t _estack; /* Symbol defined in the linker script */
+ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+ const uint8_t *max_heap = (uint8_t *)stack_limit;
+ uint8_t *prev_heap_end;
+
+ /* Initialize heap end at first call */
+ if (NULL == __sbrk_heap_end)
+ {
+ __sbrk_heap_end = &_end;
+ }
+
+ /* Protect heap from growing into the reserved MSP stack */
+ if (__sbrk_heap_end + incr > max_heap)
+ {
+ errno = ENOMEM;
+ return (void *)-1;
+ }
+
+ prev_heap_end = __sbrk_heap_end;
+ __sbrk_heap_end += incr;
+
+ return (void *)prev_heap_end;
+}
diff --git a/Core/Src/system_stm32h7xx.c b/Core/Src/system_stm32h7xx.c
new file mode 100755
index 0000000..9c59735
--- /dev/null
+++ b/Core/Src/system_stm32h7xx.c
@@ -0,0 +1,557 @@
+/**
+ ******************************************************************************
+ * @file system_stm32h7xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - ExitRun0Mode(): Specifies the Power Supply source. This function is
+ * called at startup just after reset and before the call
+ * of SystemInit(). This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock, it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#else
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#endif /* DUAL_CORE && CORE_CM4 */
+
+#if !defined(VECT_TAB_OFFSET)
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_OFFSET */
+
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting and vector table location
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+//#if defined (DATA_IN_D2_SRAM)
+// __IO uint32_t tmpreg;
+//#endif /* DATA_IN_D2_SRAM */
+//
+// /* FPU settings ------------------------------------------------------------*/
+// #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+// SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+// #endif
+// /* Reset the RCC clock configuration to the default reset state ------------*/
+//
+// /* Increasing the CPU frequency */
+// if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+// {
+// /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+// MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+// }
+//
+// /* Set HSION bit */
+// RCC->CR |= RCC_CR_HSION;
+//
+// /* Reset CFGR register */
+// RCC->CFGR = 0x00000000;
+//
+// /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+// RCC->CR &= 0xEAF6ED7FU;
+//
+// /* Decreasing the number of wait states because of lower CPU frequency */
+// if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+// {
+// /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+// MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+// }
+//
+//#if defined(D3_SRAM_BASE)
+// /* Reset D1CFGR register */
+// RCC->D1CFGR = 0x00000000;
+//
+// /* Reset D2CFGR register */
+// RCC->D2CFGR = 0x00000000;
+//
+// /* Reset D3CFGR register */
+// RCC->D3CFGR = 0x00000000;
+//#else
+// /* Reset CDCFGR1 register */
+// RCC->CDCFGR1 = 0x00000000;
+//
+// /* Reset CDCFGR2 register */
+// RCC->CDCFGR2 = 0x00000000;
+//
+// /* Reset SRDCFGR register */
+// RCC->SRDCFGR = 0x00000000;
+//#endif
+// /* Reset PLLCKSELR register */
+// RCC->PLLCKSELR = 0x02020200;
+//
+// /* Reset PLLCFGR register */
+// RCC->PLLCFGR = 0x01FF0000;
+// /* Reset PLL1DIVR register */
+// RCC->PLL1DIVR = 0x01010280;
+// /* Reset PLL1FRACR register */
+// RCC->PLL1FRACR = 0x00000000;
+//
+// /* Reset PLL2DIVR register */
+// RCC->PLL2DIVR = 0x01010280;
+//
+// /* Reset PLL2FRACR register */
+//
+// RCC->PLL2FRACR = 0x00000000;
+// /* Reset PLL3DIVR register */
+// RCC->PLL3DIVR = 0x01010280;
+//
+// /* Reset PLL3FRACR register */
+// RCC->PLL3FRACR = 0x00000000;
+//
+// /* Reset HSEBYP bit */
+// RCC->CR &= 0xFFFBFFFFU;
+//
+// /* Disable all interrupts */
+// RCC->CIER = 0x00000000;
+//
+//#if (STM32H7_DEV_ID == 0x450UL)
+// /* dual core CM7 or single core line */
+// if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+// {
+// /* if stm32h7 revY*/
+// /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+// *((__IO uint32_t*)0x51008108) = 0x000000001U;
+// }
+//#endif /* STM32H7_DEV_ID */
+//
+//#if defined(DATA_IN_D2_SRAM)
+// /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
+//#if defined(RCC_AHB2ENR_D2SRAM3EN)
+// RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+//#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+// RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+//#else
+// RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+//#endif /* RCC_AHB2ENR_D2SRAM3EN */
+//
+// tmpreg = RCC->AHB2ENR;
+// (void) tmpreg;
+//#endif /* DATA_IN_D2_SRAM */
+//
+//#if defined(DUAL_CORE) && defined(CORE_CM4)
+// /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+//#if defined(USER_VECT_TAB_ADDRESS)
+// SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+//#endif /* USER_VECT_TAB_ADDRESS */
+//
+//#else
+// if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
+// {
+// /* Enable the FMC interface clock */
+// SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+//
+// /*
+// * Disable the FMC bank1 (enabled after reset).
+// * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+// * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+// */
+// FMC_Bank1_R->BTCR[0] = 0x000030D2;
+//
+// /* Disable the FMC interface clock */
+// CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+// }
+//
+// /* Configure the Vector Table location -------------------------------------*/
+//#if defined(USER_VECT_TAB_ADDRESS)
+// SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+//#endif /* USER_VECT_TAB_ADDRESS */
+//
+//#endif /*DUAL_CORE && CORE_CM4*/
+
+ RCC->CFGR = 0x00000000;
+ SCB->VTOR = 0x90000000;
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ uint32_t common_system_clock;
+ float_t fracn1, pllvco;
+
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ common_system_clock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ common_system_clock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ common_system_clock = 0U;
+ }
+ break;
+
+ default:
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+ tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+/**
+ * @brief Exit Run* mode and Configure the system Power Supply
+ *
+ * @note This function exits the Run* mode and configures the system power supply
+ * according to the definition to be used at compilation preprocessing level.
+ * The application shall set one of the following configuration option:
+ * - PWR_LDO_SUPPLY
+ * - PWR_DIRECT_SMPS_SUPPLY
+ * - PWR_EXTERNAL_SOURCE_SUPPLY
+ * - PWR_SMPS_1V8_SUPPLIES_LDO
+ * - PWR_SMPS_2V5_SUPPLIES_LDO
+ * - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+ * - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+ * - PWR_SMPS_1V8_SUPPLIES_EXT
+ * - PWR_SMPS_2V5_SUPPLIES_EXT
+ *
+ * @note The function modifies the PWR->CR3 register to enable or disable specific
+ * power supply modes and waits until the voltage level flag is set, indicating
+ * that the power supply configuration is stable.
+ *
+ * @param None
+ * @retval None
+ */
+void ExitRun0Mode(void)
+{
+#if defined(USE_PWR_LDO_SUPPLY)
+ #if defined(SMPS)
+ /* Exit Run* mode by disabling SMPS and enabling LDO */
+ PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN;
+ #else
+ /* Enable LDO mode */
+ PWR->CR3 |= PWR_CR3_LDOEN;
+ #endif /* SMPS */
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY)
+ #if defined(SMPS)
+ /* Exit Run* mode */
+ PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
+ #else
+ PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
+ #endif /* SMPS */
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS)
+ /* Exit Run* mode */
+ PWR->CR3 &= ~(PWR_CR3_LDOEN);
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS)
+ /* Exit Run* mode */
+ PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS)
+ /* Exit Run* mode */
+ PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
+ /* Exit Run* mode */
+ PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
+ /* Exit Run* mode */
+ PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS)
+ /* Exit Run* mode */
+ PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS;
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS)
+ /* Exit Run* mode */
+ PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS;
+ /* Wait till voltage level flag is set */
+ while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+ {}
+#else
+ /* No system power supply configuration is selected at exit Run* mode */
+#endif /* USE_PWR_LDO_SUPPLY */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
generated by cgit v1.2.3 (git 2.46.0) at 2026-09-08 01:07:23 +0000