From 0cb345ed5ccbe786d0a7e7e2de740c0a07b82770 Mon Sep 17 00:00:00 2001 From: ozpv <39195175+ozpv@users.noreply.github.com> Date: Wed, 19 Aug 2026 21:34:09 -0500 Subject: sdram and ringmod effect --- Core/Src/cs4272.c | 122 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 69 insertions(+), 53 deletions(-) (limited to 'Core/Src/cs4272.c') diff --git a/Core/Src/cs4272.c b/Core/Src/cs4272.c index e7b639e..81179c7 100755 --- a/Core/Src/cs4272.c +++ b/Core/Src/cs4272.c @@ -7,42 +7,78 @@ #include "i2c.h" #include "cs4272.h" +#include "ringmod.h" volatile int32_t rx_buffer[BUFFER_SIZE] __attribute__((section(".audio_buffers"))); volatile int32_t tx_buffer[BUFFER_SIZE] __attribute__((section(".audio_buffers"))); +volatile float samples[BUFFER_SIZE] __attribute__((section(".sdram"))); const uint8_t CS4272_CONFIG[7] = { - // MODE CONTROL 1 - // single speed i2s slave + /* MODE CONTROL 1 + single speed i2s slave */ 0b00000001, - // DAC CONTROL - // no auto mute steep roll off interpolation 48 kHz de-emphasis - // Soft Ramp Up and Down and no polarity flipping - 0b00001100, - // DAC Volume & Mixing Control - // Channel B Volume = Channel A Volume Soft Ramp and Zero Cross - // a = L b = R - 0b01111001, - // Channel A volume - // 0 dB - // Binary Code Decimal Value Volume Setting - // 0000000 0 0 dB - // 0010100 20 -20 dB - // 0101000 40 -40 dB - // 0111100 60 -60 dB - // 1011010 90 -90 dB + /* DAC CONTROL + Steep Interpolation Filter + 48 kHz de-emphasis + Soft Ramp Up and Down and no polarity flip */ + 0b01101100, + /* DAC Volume & Mixing Control + Channel B Volume = Channel A Volume + Soft Ramp and Zero Cross + a = L b = R + stereo 0b01111001 */ + 0b01111000, + /* Channel A volume + 0 dB + Binary Code Decimal Value Volume Setting + 0000000 0 0 dB + 0010100 20 -20 dB + 0101000 40 -40 dB + 0111100 60 -60 dB + 1011010 90 -90 dB */ 0b00000000, - // Channel B volume - 0b00000000, - // ADC control - // I2S up to 24-bit data High Pass filter on - // bits 3:2 adc channel mute - 0b00010000, - // MODE CONTROL 2 - // power down OFF + /* Channel B volume + Muted for mono */ + 0b10000000, + /* ADC control + I2S up to 24-bit data High Pass filter on + bits 3:2 active high adc channel mute + Channel B muted */ + 0b00010100, + /* MODE CONTROL 2 + power down OFF */ 0b00000010, }; +void int32_t_to_float(int32_t *in, float *out, size_t range_min, size_t range_max) { + for (size_t i = range_min; i < range_max; ++i) { + out[i] = ((float)(in[i] << 8)) / ((float)INT32_MAX); + } +} + +void float_to_int32_t(float *in, int32_t *out, size_t range_min, size_t range_max) { + for (size_t i = range_min; i < range_max; ++i) { + out[i] = ((int32_t)(in[i] * ((float)INT32_MAX))) >> 8; + } +} + +void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) { + int32_t_to_float((int32_t *)rx_buffer, (float *)samples, 0, BUFFER_SIZE / 2); + + ringmod((float *)samples, 0, BUFFER_SIZE / 2); + + float_to_int32_t((float *)samples, (int32_t *)tx_buffer, 0, BUFFER_SIZE / 2); +} + +void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) { + int32_t_to_float((int32_t *)rx_buffer, (float *)samples, BUFFER_SIZE / 2, BUFFER_SIZE); + + ringmod((float *)samples, BUFFER_SIZE / 2, BUFFER_SIZE); + + float_to_int32_t((float *)samples, (int32_t *)tx_buffer, BUFFER_SIZE / 2, BUFFER_SIZE); +} + + HAL_StatusTypeDef CS4272_ReadRegister(uint8_t addr, uint8_t *data) { return HAL_I2C_Mem_Read(&hi2c4, CS4272_I2C_ADDR, addr, I2C_MEMADD_SIZE_8BIT, data, 1, HAL_MAX_DELAY); @@ -53,7 +89,7 @@ HAL_StatusTypeDef CS4272_WriteRegister(uint8_t addr, uint8_t data) { I2C_MEMADD_SIZE_8BIT, &data, 1, HAL_MAX_DELAY); } -void CS4272_Reset() { +void CS4272_Reset(void) { HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); HAL_Delay(10); @@ -63,20 +99,20 @@ void CS4272_Reset() { HAL_Delay(10); } -uint8_t CS4272_Init() { +uint8_t CS4272_Init(void) { CS4272_Reset(); if (HAL_I2C_IsDeviceReady(&hi2c4, CS4272_I2C_ADDR, 3, 1000) != HAL_OK) { return HAL_ERROR; } - // 5.2.1 Recommended Power-Up Sequence - // power down mode and control port enable + /* 5.2.1 Recommended Power-Up Sequence + power down mode and control port enable */ if (CS4272_WriteRegister(MODE_CONTROL_2, 0x03) != HAL_OK) { return HAL_ERROR; } - // check if device ID is correct + /* check if device ID is correct */ uint8_t id = 0; if (CS4272_ReadRegister(CHIP_ID, &id) != HAL_OK) { return HAL_ERROR; @@ -86,9 +122,9 @@ uint8_t CS4272_Init() { return 2; } - // Configure + /* Configure */ uint8_t cfg = 0; - for (uint8_t i = MODE_CONTROL_1; i < MODE_CONTROL_2; ++i) { + for (size_t i = MODE_CONTROL_1; i < CHIP_ID; ++i) { if (CS4272_WriteRegister(i, CS4272_CONFIG[i - 1]) != HAL_OK) { return HAL_ERROR; } @@ -102,25 +138,5 @@ uint8_t CS4272_Init() { } } - if (CS4272_WriteRegister(MODE_CONTROL_2, 0x02) != HAL_OK) { - return HAL_ERROR; - } - - if (CS4272_ReadRegister(MODE_CONTROL_2, &cfg) != HAL_OK || cfg != 0x02) { - return 2; - } - return HAL_OK; } - -void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) { - for(int i = 0; i < BUFFER_SIZE / 2; i++) { - tx_buffer[i] = rx_buffer[i]; - } -} - -void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) { - for(int i = BUFFER_SIZE / 2; i < BUFFER_SIZE; i++) { - tx_buffer[i] = rx_buffer[i]; - } -} -- cgit v1.2.3