diff options
| author | ozpv <39195175+ozpv@users.noreply.github.com> | 2026-08-17 00:01:22 -0500 |
|---|---|---|
| committer | ozpv <39195175+ozpv@users.noreply.github.com> | 2026-08-17 00:01:22 -0500 |
| commit | 2f60747dd3b51321903de9c51789765d41ed83e4 (patch) | |
| tree | 29b414376f804719480a98963afeeb3a66beb039 /Core/Src/dma.c | |
| parent | fddef9d200acd8f715d42f94b42722f2a2ee6600 (diff) | |
audio driver
Diffstat (limited to 'Core/Src/dma.c')
| -rwxr-xr-x | Core/Src/dma.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/Core/Src/dma.c b/Core/Src/dma.c new file mode 100755 index 0000000..86e2fa4 --- /dev/null +++ b/Core/Src/dma.c @@ -0,0 +1,58 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file dma.c
+ * @brief This file provides code for the configuration
+ * of all the requested memory to memory DMA transfers.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2026 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "dma.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure DMA */
+/*----------------------------------------------------------------------------*/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+ * Enable DMA controller clock
+ */
+void MX_DMA_Init(void)
+{
+
+ /* DMA controller clock enable */
+ __HAL_RCC_DMA1_CLK_ENABLE();
+
+ /* DMA interrupt init */
+ /* DMA1_Stream0_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
+ /* DMA1_Stream1_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
+
|